An integrated circuit chip (hereinafter referred to as an “IC” or “chip”) includes cells and inter-cell connections supported by a substrate. A cell is a group of one or more circuit elements, such as transistors, capacitors, resistors, and other basic circuit elements grouped to perform functions, both arithmetic and logical. A plurality of cells grouped together to perform functions can be referred to as a module. Some modules are designed to be reusable on different chips.
Conventionally, chip designers reuse both modules (sometimes called “macrocells”) and complex modules (sometimes called “cores” or “IP”) in order to speed the overall design process. There are many existing modules that chip designers would like to be able to incorporate into new chip designs without changes. However, the reuse of such modules introduces problems with respect to testing and verification of the overall design. While “design for test” (DFT) structures can be built into new systems, the existing modules and cores may not include test structures or may include test structures that are incompatible with the current test insertion strategies.
Historically, many different approaches have been used to make designs more testable and/or to actually insert test structures into the design, including both manual and automated approaches. Such test insertion is typically performed separately from functional Register Transfer Language (RTL) design of chips. Manual test insertion requires extra design work in a design process that is already very complex and lengthy. The investment made in manual test insertion can be risky and is susceptible to changes because test insertion strategies change over time. Since RTL coding is typically a manual process, hard-coding specific test strategies into the RTL code is not desirable. Moreover, there are commercially available design tools that are adapted for inserting test structures into a gate-level netlist, so such manual coding is not necessary.
Such automated test insertion is advantageous in that the modules can be reused as-is without design changes for test insertion. Additionally, automated test insertion can be easily adapted to different test insertion flows as such flows evolve. Currently, automated test insertion is performed at the gate level, in part, due to the relative ease with which tools can be developed to insert test structures at this level as compared to automated test insertion at the RTL level. Test insertion is also performed at the gate level because, conventionally, physical design flows are based on what is called gates-to-placed gates timing closure flow.
A Gates-to-Placed-Gates flow is used when an already available synthesized and “test ready” netlist is available from a logic synthesis tool, and a physical design and placement system is then used to place the design and to perform physical scan ordering. The design is first synthesized with scan from the RTL in the logic synthesis tool using wire-load models to estimate timing. The synthesized netlist is placed and optimized in the physical design and placement system. Scan-chain ordering is performed within the physical design and placement system environment to stitch the scan chains based on physical information, thereby achieving timing closure and optimizing the layout for routability. The gates-to-placed-gates flow is the traditional design flow where RTL is synthesized to create a gate level netlist, which is then timing closed using estimated interconnect loading before being physically placed. The Gates-to-Placed-Gates flow is currently used when the starting point for the reusable module is a gate-level implementation. When used by itself, Gates-to-Placed-Gates flow is sub-optimal for state-of-the-art chip design. In particular, it is sub-optimal because the logic synthesis step does not take into account the effects of physical placement of the gates, but instead uses only a wireload to estimate the effects.
Another type of design flow is called RTL-to-Placed-Gates flow. RTL-to-Placed-Gates flow uses RTL source code, timing information, Design Rule Check (DRC) constraints, design libraries, and DFT information, and the like to determine and generate legalized gate placement for routing. The RTL-to-Placed-Gates flow incoporates physical characteristics and timing information as part of its mapping and placement from RTL-to-Gates. This type of flow uses traditional scan synthesis flow within a physical compiler environment to perform scan chain ordering. In most instances, the test insertion is performed using a gate-level representation. RTL-to-Placed Gates flow is a more optimal design flow for contemporary chip designs than Gates-to-Placed-Gates flow.
It is not desirable to do gate-level test insertion, in the traditional sense, after the RTL-to-Placed-Gates flow. Specifically, adding test logic to a placed netlist will disturb the timing closure that has already been completed, because some cells will need to be moved to insert the additional test logic. It is desirable to perform test insertion at the RTL level, because all logic cells (both functional and test related) are accounted for as the placement is completed during synthesis. However, RTL level test insertion is difficult. Typically, test insertion flows (including RTL-to-Placed-Gates) do some sort of mapping from RTL to logic cells and then insert tests at the logic cell level.
Therefore, there is an ongoing need for improvements in computer-aided test insertion systems and methods for integrated circuit design. Embodiments of the present invention provide solutions to these and other problems and provide advantages over the prior art.